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TM 55-4920-383-13&P
e.
Resistance measurement is under the control of the RESISTANCE FUNCTION switch
(11). The RESISTANCE FUNCTION switch (11) selects the resistance measurement mode
(for example, resistance measurement across the EXT RES terminals (10), or measurement
across the UNSH B and COAX A Test Set connectors (18), etc). The output of the
RESISTANCE FUNCTION switch (11) feeds the resistance-to-de converter.
to-dc converter generates a dc voltage proportional to the resistance being
The resistance-
measured. This
dc voltage is scaled by the RESISTANCE RANGE switch (12). The scaled voltage is applied
to the analog-to-digital converter when the DISPLAY SELECT switch (8) is in the RES (MEG)
position. The analog-to-digital converter converts the dc voltage (which is proportional to
the resistance being measured) to a digital code.
This code is applied to the digital readout
which, in turn, displays the value of the resistance being measured (in megohms).
f .
The Test Set has built-in stable, standard capacitors and standard resistors used
for verification and calibration of the Test Set accuracy. The standard capacitors are
routed through the CAPACITANCE RANGE switch (6) and are measured by circuitry asso-
ciated with capacitance measurement as previously described. Likewise, the standard
resistors are routed through the RESISTANCE RANGE switch (12) and are measured by the
circuitry associated with the resistance measurement as previously described.
2-12.
Schematic Diagram Description.
The schematic diagram, figures FO-1 thru FO-6 is a detailed logic and circuit
diagram of the Test Set. As an aid to understanding of the Test Set, the diagram is
keyed, utilizing squared letter references
, to timing diagrams figures 2-4
and 2-5 and logic tables figures 2-6 thru 2-13. Logic levels are defined as follows:
Logic 0: less than 0.4VDC
Logic 1: greater than 2.4VDC
2-23
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